The present invention relates to the art of semiconductor memories. It finds particular application in conjunction with static RAMs and will be described with particular reference thereto. It is to be appreciated, however, that the invention may also find application in conjunction with other memory and semiconductor devices
Heretofore, a random access memory has commonly included a large array of memory cells. The memory cells have been commonly addressed by a combination of a row or x-address and a column or y-address. A word driver or x-decoder received a memory address and enabled a corresponding row or word line of memories to be accessed. A column or y-decoder and a column select switch also received the address and enabled one of the columns. The memory cell at the intersection of the enabled column or bit line and the enabled row or word line could be written into or read. Data read from the cell was conveyed to a common data bus and amplified by sensing amplifiers.
As the memories became larger in scale, an increased number of memory cells were connected to each word line and an increased number of word lines were provided. This increased the current consumption each time a memory was activated and decreased the operating speed. If the word lines were shortened, the number of word lines, hence, the height of the columns would increase resulting in similar problems.
To reduce the power consumption and increase the operating speed, the memory was divided into a plurality of mats. The x-decoder or word driver selected a main word line, i.e. corresponding word line in each mat. Group word logic cells were added to select only a group word line in one of the mats. This reduced the length of the physically enabled word line which reduced power consumption and increased speed.
The length of the word line was further reduced by using double word line architecture. The double word line architecture effectively divided each mat in half such that the effective length of each word line was halved again. See for example, U.S. Pat. No. 4,554,646 issued Nov. 19, 1985 to Yoshimoto, et al.
One of the problems with the double word line architecture is that it made no improvement in the speed or power consumption attributable to the y or column address. To improve the column efficiency, the common data bus was divided into a plurality of segments. In the double word architecture, a segment was provided for each of the effective or half mats. That is, in a memory cell having eight mats which were each effectively divided in two by the double word architecture, sixteen common data bus segments were required. A corresponding large number of sensing amplifiers were required to connect each common data bus segment with an output data bus. For an eight bit memory, sixteen sensing amplifiers were commonly required per segment. These amplifiers not only increased the complexity of the memory, but also had a deleterious effect on its speed and power consumption.
The present invention contemplates a new and improved memory construction which overcomes the above referenced problems and others.